1. Field of the Invention
The present invention relates to the field of testing dielectrics. More particularly, the present invention relates to a device for testing a dielectric, e.g., a tunnel oxide, at the wafer level. The present invention also provides for a method of performing the testing using such a device. More particular yet, the present invention involves a localized heating element and local temperature sensor at the wafer level used to accelerate endurance testing of dielectric structures while providing accurate predictions of dielectric reliability and ultimate product endurance performance.
2. Description of the Prior Art
Production of integrated circuitry (IC) continues to increase throughout the world in response to the explosive growth of the electronics industry. Such IC's are commonly fabricated in multiple layers on a silicon wafer. The fabrication processes such as photo-lithographic etching or lost-wax methods typically involve many steps including depositing layers only microns thick of various metals, coating photo-resist, or otherwise etch-resistant, materials in circuitry patterns, etching away layer portions, bombarding such layer portions with ions, and repeating such steps in various manners to produce the IC of any given design. For example, an IC containing a metal-oxide-semiconductor (MOS) device has a thin layer of oxide over which a layer of conductive gate material, e.g., polysilicon, is formed and then defined. The MOS device source and drain are then formed, either by photo-lithography or by using the defined gates as a self-aligning mask. In some IC's, a capacitor may be formed by forming a layer of conductive material, e.g., polysilicon, over a thin layer of oxide. Normal back-end processing completes the fabrication of the IC.
Such fabrication is time-consuming and can take many hours, days, or even longer, depending on complexity, before a finished IC is ready for use within a subsequent electronic product. As the IC includes many microscopic elements that are sensitive to even the slightest impurities, IC fabrication occurs under strict clean-room conditions. Improper layering or etching or the introduction of impurities during fabrication results in weak oxide layers. For example, the silicon wafers may have been cleaned with wet chemicals, or contamination may have been present in the gate oxide tube used during fabrication. In any event, such defects may exist randomly anywhere within the IC structure, and will affect the reliability of every structure formed on the wafer that utilizes thin oxide layers, e.g., every MOS device and every capacitor. Additionally, damage may occur to the oxide upon its being subjected to an excessively charged environment. The oxide is especially vulnerable to charge-damage during fabrication steps such as plasma etching, plasma ashing, plasma deposition, ion implantation, and sputtering. Both contaminants and charge-damage can lead to oxide breakdown and ultimately to the failure of any product in which the IC containing the degraded oxide is utilized. As fabrication is performed on a mass-production scale, such IC failure can be extremely costly when it occurs at the product level. Accordingly, IC's typically undergo significant testing prior to their being used in an electronic product. Ideally, testing results should be ascertained as early in fabrication as possible so that corrections can be made without wasting time and materials.
Monitoring of the robustness of a dielectric film is normally done by stressing it to breakdown. A conventional stress method involves the application of a voltage to electrodes in which the dielectric film is sandwiched between. The parameter monitored could be the time dependent dielectric breakdown (TDDB) or the amount of charge that passed through the dielectric before breakdown (Charge-to-breakdown, Q.sub.bd). The value of the TDDB or Q.sub.bd provide an indication of the quality of the film tested. By sampling the wafers during their processing, the fabrication process can be monitored for variations in dielectric quality. Accordingly, the fabrication process may be adjusted so as to maintain dielectric quality within tolerable limits. While this method of monitoring is widely used for predicting the ultimate threshold for dielectric breakdown, there are some problems with the method. The stress is normally performed at high electric field or current to induce failure within reasonable short time and it is widely known that it does not predict the endurance of nonvolatile memory such as EEPROM, EPROM, and FLASH. Endurance is the number of program-erase cycles it takes before breakdown of the dielectric occurs. In spite of its limited usefulness, Q.sub.bd and TDDB has typically been used to predict non-volatile memory endurance for the lack of better method.
An essential part of estimating operable life of a semiconductor device has been bum-in testing. Generally, burn-in tests are conducted using burn-in boards and a burn-in test chamber. IC's are placed within sockets in the burn-in boards and subsequently placed in the burn-in chamber. It is well known in the field of integrated circuit testing that burn-in testing of semiconductor components is a slow and expensive process, requiring very large test chambers. Simply put, burn-in testing involves the accelerated aging of an IC to determine to a reasonable certainty whether that IC will perform essentially as expected for its anticipated life. In practice, burn-in testing involves powering-up the IC, running test signals to the circuitry, and evaluating the IC response. This testing is conducted at elevated temperatures within the burn-in chamber for specified periods of time in a way that exposes "infant mortality failures" (those ICs that fail as a result of fabrication variations and that fail early in the test procedure, indicating much-earlier-than-expected failure if used under actual operating conditions). Thus from this TDDB method, Q.sub.bd is ascertained. Reaching Q.sub.bd early in the test procedure indicates a high infant mortality. Burn-in testing can also be used to expose "freak failures" (those IC's that do not apparently have fabrication flaws but that nevertheless fail at an unexpectedly early time in their service lives).
For the most part, present IC burn-in test procedures involve subjecting the IC's to test conditions after they are permanently connected with a number of other electronic devices as part of an entire module or package. As a result, failure of the particular IC under test means failure of the entire module or package and that entire package must be discarded. Needless to say, such IC failures are expensive. The recent expansion in the use of multichip packages with interconnected devices compounds the potential loss caused by the failure of a single chip under burn-in.
The device of Hashinaga et al. (U.S. Pat. No. 5,406,212) relates to burn-in testing. Apparently, the device is designed to reduce the burn-in time required. It includes an on-chip temperature sensor to sense junction temperature. The burn-in chamber's temperature is then controlled relative to the on-chip sensor. In that regard, the burn-in time may be optimized. However, the Hashinaga system does not provide localized heating that can be used to determine in a relatively short time whether particular semiconductor junctions of the circuitry under test are deficient. Instead, as with all burn-in testing, the Hashinaga system is die-rather than structure-responsive. It fails, therefore, to reduce in a substantial way the expense and time involved in circuit testing.
Accordingly, the prior art provides numerous ways to test complete semiconductor circuitry prior to insertion into packaging. However, that testing is time consuming and requires the expenditure of considerable energy to regulate the test temperature for the circuitry under test, whether that regulation involves heating, or, for bipolar devices, cooling. In no way does the prior art address the need to be able to effectively conduct localized testing, and, preferably, accelerated localized testing, particularly at the wafer level of the critical oxide structures that often define the quality of the circuitry. In that regard, it is necessary to ensure that any heat applied to localized structures is directed to such structures when and where required in order to minimize any effects on sub-circuitry that is not under analysis.
Therefore, what is needed is a wafer-level dielectric test apparatus and process that can be used to accurately evaluate oxide structure endurance that will closely match endurance of the actual product that include such structures, when that product is used as intended. What is also needed is a wafer-level dielectric test system with good predictability that minimizes test time through some form of acceleration. Further, what is needed is a wafer-level test system that provides reliable test-temperature management in order to ensure rapid and accurate heat input when required and where required.